A DRAM (Dynamic Random Access Memory) is mainly used as a main memory in a personal computer or a server. It is common that the DRAM used for a main memory is mounted in advance on a memory module such as a DIMM, to facilitate operations of expansion.
A memory module of a type called an Unbuffered memory module is widely used. However, the Unbuffered memory module employs a stab system for connecting all memory modules to the same channel. Therefore, when the number of memory modules is increased, the load on the channel increases accordingly. When the number of memory modules is increased, the number of branch points on the transmission line increases, and the signal quality is lowered.
Therefore, when a high data transfer rate is required, a memory module of a type called a Fully Buffered memory module is used (Japanese Patent Application Laid-open No. 2006-268683). According to the Fully Buffered memory module, plural memory modules are connected in cascade. Therefore, the Fully Buffered memory module has an advantage in that the load applied to the channel does not increase even when the number of used memory modules increases. Because no branch point is generated on the transmission line, high signal quality can be secured.
In the Fully Buffered memory module, a memory buffer called an AMB (Advanced Memory Buffer) is mounted on the module substrate, in addition to plural memory chips. The memory buffer buffers an address, data, and a command supplied from the memory controller, and transfers them to memory chips on the memory module.
As explained above, in the Fully Buffered memory module, the memory buffer and plural memory chips are mounted on the module substrate. Because it is desired to mount as many memory chips as possible on the module substrate, memory chips are often mounted on a position opposite to the memory buffer, that is, on the back surface of the memory buffer, via the module substrate.
FIG. 6 is a schematic diagram for explaining a general wiring method in a memory module having memory chips mounted on the back surface of the memory buffer. In FIG. 6, memory chips MC1 and MC2 are those mounted on the back surface of a memory buffer MB. On the other hand, memory chips MC3 to MC18 are those mounted at positions on different planes from that of the memory buffer MB.
According to the wiring method shown in FIG. 6, the output signal from the memory buffer MB is first supplied to a branch point B0 via a wiring part A0, and this output signal is distributed to wiring parts A10 and A20. The output signal on the wiring part A10 is distributed to wiring parts A11 and A12 at a branch point B1. Similarly, the output signal on the wiring part A20 is distributed to wiring parts A21 and A22 at a branch point B2.
As shown in FIG. 6, the wiring part A11 is that for supplying a signal to a memory chip MC1, and a wiring part A12 is that for supplying a signal to memory chips MC3, MC5, MC7, MC9, MC11, MC13, MC15, and MC17. The wiring part A21 is that for supplying a signal to a memory chip MC2, and a wiring part A22 is that for supplying a signal to memory chips MC4, MC6, MC8, MC10, MC12, MC14, MC16, and MC18.
The wiring parts A11 and A21 are wirings exclusive for the memory chips MC1 and MC2, and therefore, have small load and short wiring lengths, respectively. Consequently, there is a problem in that the output signal from the memory buffer MB is reflected from terminals of the memory chips MC1 and MC2 connected to the wiring parts A11 and A21, and a signal waveform is distorted.
FIG. 7 is a schematic graph showing a voltage change appearing in the wiring part A12 when a step pulse is output from the memory buffer MB.
As shown in FIG. 7, when a step pulse is output from the memory buffer MB, the voltage of the wiring part A12 once increases to V1, maintains V1 during a period t1, and then increases to V2. In other words, the waveform becomes step-like. This waveform is formed because the step pulse reaching the wiring part A12 includes a component that directly reaches the wiring part A12 via the wiring parts A0 and A10, and a component that is reflected from the terminal of the memory chip MC1 connected to the wiring part A11. Consequently, when the length of the wiring part A11 is longer, the period t1 during which the voltage is kept at V1 becomes longer, and the waveform is distorted large.
Accordingly, when the memory buffer MB outputs a complementary signal, a cross-point becomes unclear, as shown in FIG. 8. As a result, in the memory module of the type using both edges of the clock like the DDR DRAM, a high-speed data transmission becomes difficult.
To suppress the reflection of a signal from the memory chips MC1 and MC2, there is a method of connecting terminating resistors R1 and R2 to the wiring parts A11 and A12, as shown in FIG. 9. However, the terminating resistor takes a very large area on the module substrate, and therefore, it is not realistic to add the terminating resistor to a part near the memory buffer MB (the center of the module substrate) Further, the wiring parts A11 and A12 are relatively near the memory buffer MB. Therefore, when the terminating buffers R1 and R2 are connected to this part, the output power of the memory buffer MB needs to be increased. When the output power of the memory buffer MB is increased, the reflections of the signal from the memory chips MC1 and MC2 increase. Consequently, it becomes difficult to sufficiently suppress the reflections of the signal.
Furthermore, as shown in FIG. 10, there is also a method that the front surface and the back surface of the module substrate are separately connected, instead of using wirings branched to the memory chips MC1 and MC2. That is, the wiring branched to the memory chips MC1 and MC2 is not necessary, when the memory chips MC3 to MC10 mounted on the front surface of the module substrate are connected in cascade using wiring parts A31 and A32, and when the memory chips MC1, MC2, and MC11 to MC18 mounted on the back surface of the module substrate are connected in cascade using wiring parts A41 and A42.
However, when this connection is carried out, there arises a difference between the wiring lengths from the memory buffer MB to a pair of memory chips, that is, two opposite memory chips (the memory chips MC3 and MC11, for example) that sandwich the module substrate. Therefore, it becomes considerably complex to adjust a delay in the memory buffer MB and the number of wirings also increases. Therefore, this method is not practical.